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E2L0050-29-61 Semiconductor
Semiconductor MSM5416126A
DESCRIPTION
This version: Jun. 1999 MSM5416126A Previous version: Jan. 1998
131,072-Word 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
The OKI MSM5416126A is a 128K-word 16-bit dynamic RAM fabricated in OKI's CMOS silicon gate technology. The MSM5416126A achieves high integration, high-speed operation, and lowpower consumption due to quadruple polysilicon double metal CMOS. The MSM5416126A has conventional two CAS type 256K 16 DRAM compatible pinout. The MSM5416126A is available in a 40-pin plastic SOJ or 44/40-pin plastic TSOP.
FEATURES
* Fast Page Mode with Extended Data Out * Byte wide control: 2 CAS control * 131,072-word 16-bit organization * Pin compatible with 2 CAS type 256K 16 DRAM * Single 5 V power supply, 10% tolerance * CAS before RAS refresh, Hidden refresh, RAS only refresh capability * Refresh: 512 cycles/8 ms * Package options: 40-pin 400 mil plastic SOJ (SOJ40-P-400-1.27) (Product : MSM5416126A-xxJS) 44/40-pin 400 mil plastic TSOP (Type II) (TSOPII44/40-P-400-0.80-K) (Product : MSM5416126A-xxTS-K) xx indicates speed rank.
PRODUCT FAMILY
Family MSM5416126A-40 MSM5416126A-45 MSM5416126A-50 MSM5416126A-60 Access Time (Max.) tRAC tAA tCAC tOEA 40 ns 22 ns 14 ns 14 ns 45 ns 24 ns 14 ns 14 ns 50 ns 26 ns 14 ns 14 ns 60 ns 30 ns 15 ns 15 ns Cycle Time (Min.) tRC 75 ns 85 ns 100 ns 120 ns tHPC 20 ns 20 ns 22 ns 25 ns Power Dissipation Operating (Max.) Standby (Max.) 770 mW 715 mW 660 mW 605 mW 11 mW
1/22
Semiconductor
MSM5416126A
PIN CONFIGURATION (TOP VIEW)
VCC 1 40 VSS DQ0 2 DQ1 3 DQ2 4 DQ3 5 VCC 6 39 DQ15 38 DQ14 37 DQ13 36 DQ12 35 VSS DQ4 7 DQ5 8 DQ6 9 34 DQ11 33 DQ10 32 DQ9 31 DQ8 30 NC VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 21 22 DQ7 10 NC 11 NC 12 29 LCAS 27 OE 26 A8 25 A7 24 A6 23 A5 22 A4 21 VSS 40-Pin Plastic SOJ 44/40-Pin Plastic TSOP (II) (K Type) WE 13 28 UCAS RAS 14 NC 15 A0 16 A1 17 A2 18 A3 19 VCC 20 NC NC WE RAS NC A0 A1 A2 A3 VCC
44 43 42 41 40 39 38 37 36 35 32 31 30 29 28 27 26 25 24 23
VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS
Pin Name A0 - A8 RAS LCAS UCAS DQ0 - DQ15 WE OE VCC VSS NC
Function Address Input Row Address : A0 - A8 Column Address : A0 - A7 Row Address Strobe Lower Byte Column Address Strobe Upper Byte Column Address Strobe Data - Input / Data - Output Write Enable Output Enable Power Supply (5 V) Ground (0 V) No Connection
Note: The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/22
Semiconductor
MSM5416126A
BLOCK DIAGRAM
OE RAS LCAS UCAS
Burst Address Counter Column Address Buffers Internal Address Counter Row Address Buffers Timing Generator
WE
I/O Controller I/O Controller 8 Output Buffers 8
DQ0 - DQ7
8 8 Column Decoders 8 I/O Selector 16 Input Buffers Input Buffers 8
A0 - A8
Refresh Control Clock
Sense Amplifiers
16
8 9 9 Row Decoders Word Drivers Memory Cells 8
8
DQ8 - DQ15
Output Buffers 8
VCC
On-chip VBB Generator
VSS
FUNCTION TABLE
Input Pin RAS H L L L L L L L L LCAS * H L H L L H L L UCAS * H H L L H L L L WE * * H H H L L L H OE * * L L L H H H H High-Z High-Z DOUT High-Z DOUT DIN Don't Care DIN High-Z DQ Pin DQ0 - DQ7 DQ8 - DQ15 High-Z High-Z High-Z DOUT DOUT Don't Care DIN DIN High-Z Function Mode Standby Refresh Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write --
* : "H" or "L"
3/22
Semiconductor
MSM5416126A
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Voltage on Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT IOS PD Topr Tstg Condition Ta = 25C Ta = 25C Ta = 25C -- -- Rating -1.0 to 7.0 50 1 0 to 70 -55 to 150 Unit V mA W C C
Recommended Operating Conditions
Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 4.5 0 2.4 -1.0 Typ. 5.0 0 -- -- Max. 5.5 0 6.5 0.8
(Ta = 0C to 70C) Unit V V V V
Capacitance
Parameter Input Capacitance (A0 - A8) Input Capacitance (RAS, LCAS, UCAS, WE, OE) Output Capacitance (DQ0 - DQ15) Symbol CIN1 CIN2 CI/O Typ. -- -- --
(VCC = 5 V 10%, Ta = 25C, f = 1 MHz) Max. 7 7 10 Unit pF pF pF
4/22
Semiconductor DC Characteristics
MSM5416126A
(VCC = 5 V 10%, Ta = 0C to 70C) Parameter Output High Voltage Output Low Voltage Input Leakage Current Symbol VOH VOL ILI Condition IOH = -1.0 mA IOL = 1.0 mA MSM5416126A MSM5416126A MSM5416126A MSM5416126A -40 -45 -50 -60 Unit Note Min. Max. Min. Max. Min. Max. Min. Max. 2.4 0 VCC 0.4 10 2.4 0 -10 VCC 0.4 10 2.4 0 -10 VCC 0.4 10 2.4 0 -10 VCC 0.4 10 V V mA
0 V VI 6.5 V ; All other pins not -10 under test = 0 V DQi Disable -10 0 V VO 5.5 V RAS, CAS Cycling, tRC = Min. RAS, CAS = VIH RAS = Cycling, CAS = VIH, tRC = Min. RAS = VIH, CAS = VIL, Dout = Enable RAS = Cycling, CAS before RAS RAS = VIL, CAS Cycling, tPC = Min. --
Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS Only Refresh) Power Supply Current (Standby)
ILO
10
-10
10
-10
10
-10
10
mA
ICC1
140
--
130
--
120
--
110
mA 1, 2
ICC2
--
2
--
2
--
2
--
2
mA
1
ICC3
--
140
--
130
--
120
--
110
mA 1, 2
ICC5
--
5
--
5
--
5
--
5
mA
1
Average Power Supply Current ICC6 (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode)
--
140
--
130
--
120
--
110
mA 1, 2
ICC7
--
130
--
130
--
120
--
110
mA 1, 3
Notes :
1. Specified values are obtained with output open. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH.
5/22
Semiconductor AC Characteristics (1/2)
Parameter Random Read or Write Cycle Time Read Modify Write Cycle Time Hyper Page Mode Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from OE Access Time from CAS Precharge Data Hold After CAS Low Output Buffer Turn-off Delay Time OE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode) RAS Hold Time RAS Hold Time referenced to OE CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address Hold Time from RAS Column Address to RAS Lead Time
MSM5416126A
(VCC = 5 V 10%, Ta = 0C to 70C) Note 1, 2, 3
Symbol
MSM5416126A MSM5416126A MSM5416126A MSM5416126A -40 -45 -50 -60 Unit Note Min. Max. Min. Max. Min. Max. Min. Max. 75 115 20 60 -- -- -- -- -- 0 3 3 3 2 -- 25 40 14 8 5 8 40 5 18 12 0 8 0 6 30 22 -- -- -- -- 40 14 22 14 26 -- -- 8 8 35 8 -- 10,000 -- -- -- 10,000 -- -- 26 18 -- -- -- -- -- -- 85 130 20 60 -- -- -- -- -- 0 3 3 3 2 -- 30 45 14 8 6 8 45 5 18 13 0 8 0 6 30 24 -- -- -- -- 45 14 24 14 27 -- -- 8 8 35 8 -- 10,000 -- -- -- 10,000 -- -- 31 21 -- -- -- -- -- -- 100 145 22 65 -- -- -- -- -- 0 3 3 3 2 -- 40 50 14 10 7 9 50 5 20 15 0 10 0 8 35 26 -- -- -- -- 50 14 26 14 29 -- -- 8 8 35 8 -- 10,000 -- -- -- 10,000 -- -- 36 24 -- -- -- -- -- -- 120 165 25 80 -- -- -- -- -- 0 3 3 3 2 -- 50 60 15 10 8 12 60 5 20 15 0 10 0 10 45 30 -- -- -- -- 60 15 30 15 34 -- -- 10 10 35 8 -- ns ns ns ns ns 4, 9, 10 ns ns ns 4, 9, 10 ns ns ns ns ns ms ns 5 5 4, 9 ns 4, 10
tRC tRWC tHPC tRAC tCAC tAA tOEA tCPA tCOH tOFF tOEZ tT tREF tRP tRAS tRASP tRSH tROH tCAS tCSH tCRP tRCD tRAD tASR tRAH tASC tCAH tAR tRAL
Fast Page Mode Read Modify Write Cycle Time tPRWC
Output Low Impedance Time from CAS tCLZ
10,000 ns -- -- -- -- -- 45 30 -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns 11 11 12 9 10 14
40 100,000 45 100,000 50 100,000 60 100,000 ns
CAS Precharge Time (Fast Page Mode) tCP
10,000 ns
6/22
Semiconductor AC Characteristics (2/2)
Parameter Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Pulse Width Write Command Hold Time from RAS OE Command Hold Time Write Command to CAS Lead Time Write Command to RAS Lead Time Output Buffer Turn-off Delay Time from WE Output Buffer Turn-off Delay Time from CAS Data to CAS Delay Time Data to OE Delay Time Data-in Set-up Time Data-in Hold Time Data-in Hold Time referenced to RAS OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time OE "L" to CAS "H" Lead Time CAS "H" to OE "L" Lead Time Hi-Z Command Pulse Width CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS)
Symbol
MSM5416126A
(VCC = 5 V 10%, Ta = 0C to 70C) Note 1, 2, 3 MSM5416126A MSM5416126A MSM5416126A MSM5416126A -40 -45 -50 -60 Unit Note Min. Max. Min. Max. Min. Max. Min. Max. tRCS tRCH tRRH tWCS tWCH tWP tWCR tOEH tCWL tRWL tWEZ tCEZ tDZC tDZO tDS tDH tDHR tOED tCWD tAWD tRWD tOCH tCHO tOEP tRPC tCSR tCHR 0 0 0 0 8 7 30 8 7 14 3 3 0 0 0 7 30 8 28 38 60 10 10 10 0 10 10 -- -- -- -- -- -- -- -- -- -- 15 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 0 0 8 8 30 8 8 14 3 3 0 0 0 8 30 8 30 40 65 10 10 10 0 10 10 -- -- -- -- -- -- -- -- -- -- 15 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 0 0 9 9 35 9 9 14 3 3 0 0 0 9 35 8 32 44 70 10 10 10 0 10 10 -- -- -- -- -- -- -- -- -- -- 15 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 0 0 10 10 45 10 12 15 3 3 0 0 0 10 45 10 35 50 80 10 10 10 0 10 10 -- -- -- -- -- -- -- -- -- -- 15 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns 11 ns 6, 11 ns 6
ns 8, 11 ns ns ns ns ns ns ns ns ns ns ns 7, 11 ns 7, 11 ns ns ns ns ns ns ns ns ns ns ns 11 11 12 8 8 8 5 5 13 11
7/22
Semiconductor Notes:
MSM5416126A
1. An initial pause of 200 ms is required after power-up, followed by any 8 RAS cycles. (Example : RAS-only-refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 1 TTL load and 50 pF. Output timing reference levels are VOH = 2.0 V and VOL = 0.8 V. 5. tCEZ (Max.), tOFF (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the outputs achieve the open circuit condition and are not referenced to output voltage levels. 6. tRCH or tRRH must be satisfied for a read cycle. 7. These parameters are referenced to UCAS, LCAS, leading edge in an early write cycle, and to WE leading edge in an OE control write cycle or a read modify write cycle. 8. tWCS, tCWD, tRWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (Min.), the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD (Min.) , tRWD tRWD (Min.) and tAWD tAWD (Min.) , the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 9. Operation within the tRCD (Max.) limit insures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then access time is controlled by tCAC. 10. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (Max.) limit, then access time is controlled by tAA. 11. These parameters are determined by the falling edge of UCAS or LCAS, whichever is earlier. 12. These parameters are determined by the rising edge of UCAS or LCAS, whichever is later. 13. tCWL should be satisfied by both UCAS and LCAS. 14. tCP is determined by the time both UCAS and LCAS are high. 15. Input levels at the AC testing are 3.0 V/0.5 V.
8/22
Semiconductor
MSM5416126A
TIMING WAVEFORM
Read Cycle (RAS Output Control)
RAS
UCAS LCAS
A0 - A8
WE
OE
DQ0 - 7
DQ8 - 15
,, ,
tRC tRAS tRP tCRP tCRP tCSH tRCD tRSH tCAS tAR tRAD tRAL tASR tRAH tASC tCAH Row Column tRCS tRRH tROH tOEA tOEZ tCAC tCEZ tAA Open Valid Data tRAC Open Valid Data "H" or "L"
9/22
Semiconductor
Read Cycle (CAS Output Control)
RAS
UCAS LCAS
A0 - A8
WE
OE
DQ0 - 7
DQ8 - 15
,, ,
tRC tRAS tRP tCRP tCRP tCSH tRCD tRSH tCAS tAR tRAD tRAL tASR tRAH tASC tCAH Row Column tRCS tRRH tROH tOEA tOEZ tCAC tCEZ tAA Open Valid Data tRAC Open Valid Data "H" or "L"
MSM5416126A
10/22
Semiconductor
Early Write Cycle (LCAS and UCAS Active)
RAS
UCAS LCAS
A0 - A8
WE
OE
DQ0 - 7
DQ8 - 15
,, , ,, ,
tRC tRAS tRP tCRP tCSH tRCD tRSH tCAS tAR tRAD tRAL tASR tRAH tASC tCAH Row Column tCWL tRWL tWP tWCR tWCS tWCH tDHR tDS tDH Valid Data tDS tDH Valid Data "H" or "L"
MSM5416126A
11/22
Semiconductor
Late Write Cycle (LCAS and UCAS Active)
RAS
UCAS LCAS
A0 - A8
WE
OE
DQ0 - 7
DQ8 - 15
,, , , ,,
tRC tRAS tRP tCRP tCSH tRCD tRSH tCAS tAR tRAD tRAL tASR tRAH tASC tCAH Row Column tRCS tCWL tRWL tWP tWCR tOEH tOED tDS tDH Valid Data tOED tDS tDH Valid Data "H" or "L"
MSM5416126A
12/22
Semiconductor
Read Modify Write Cycle (LCAS and UCAS Active)
RAS
UCAS LCAS
A0 - A8
WE
OE
DQ0 - 7
DQ8 - 15
,, , ,, , ,
tRWC tRAS tRP tCRP tCSH tRCD tRSH tCAS tAR tRAD tRAL tASR tRAH tASC tCAH Row Column tAWD tRCS tCWL tRWL tWP tRWD tDZO tCWD tOEA tOEZ tOEH tOED tCAC tDZC tCLZ tDS tDH Out In tRAC tCLZ tDS tDH Out In "H" or "L"
MSM5416126A
13/22
Semiconductor Fast Page Mode Read Cycle with Extended Data Out
tRASP RAS
MSM5416126A
tRP
, ,
tCRP tRCD tCP tCP UCAS LCAS tCAS tCAS tCAS tRAD tASR tRAH tAR tASC tCAH Column tASC tCAH tASC tRAL tCAH A0 - A8 Row Column Column tRCS tRCH WE tAA tRRH tOEA OE tCAC tCAC tCAC tCOH tCOH tOFF tOEZ DQ0 - 7 Open tRAC Valid Data tCPA tAA Valid Data Valid Data tCPA tAA Valid Data Valid Data DQ8 - 15 Open Valid Data "H" or "L"
tCSH
tHPC
tRSH
14/22
Semiconductor
Fast Page Mode Read High-Z Operation
tRASP
tRP

RAS tAR tCSH tCRP tRCD UCAS LCAS tRAD tASR tRAH Row tASC A0 - A8 tRCS WE tRAC OE tAA DQ0 - 7
Open
tHPC tCP tCAS tCP tCAS tCP
tRSH tCRP tCAS tRAL
tCAS
,
tCAH tASC tCAH Column tASC tCAH Column tASC tCAH Column Column tRRH tRCH tRCS tRCH tCHO tOCH tWP tOEA tCAC tOEP tOEP tAA tCAC tCAC tCPA tAA tCAC tCOH tOEZ tOEA tOEZ tOEA tWEZ tAA tCEZ
Valid Data Valid Data Valid* Data Valid* Data Valid Data
MSM5416126A
DQ8 - 15
Open
Valid Data
Valid Data
Valid* Data
Valid* Data
Valid Data
15/22
* : Same Data,
"H" or "L"
Semiconductor Fast Page Mode Early Write Cycle
tRASP RAS
MSM5416126A
tRP
, ,, ,,,
tCRP tCSH tHPC tRCD tCP tCP tRSH UCAS LCAS tCAS tCAS tCAS tAR tRAD tCAH tRAL tASR tRAH tASC tASC tCAH tASC tCAH A0 - A8 Row Column Column Column tCWL tCWL tCWL tWCS WE tWP tWCH tWCS tWP tWCH tWCS tWP tWCH OE tDS tDH tDS tDH tDS tDH DQ0 - 7
Input Data
Input Data tDS
Input Data tDS
tDS
tDH
tDH
tDH
DQ8 - 15
Input Data
Input Data
Input Data
"H" or "L"
16/22
Semiconductor Fast Page Mode Read Modify Write Cycle
MSM5416126A
,, , ,
tRASP tRP RAS tAR tCSH tCRP tRCD tCAS tCP tPRWC tCAS tCP tRSH tCAS UCAS LCAS tRAD tASR tRAH Row tASC tCAH tASC tCAH tASC tRAL tCAH A0 - A8 Column tAWD Column tAWD Column tAWD tCWL tCWL tCWL WE tCWD tCWD tCWD tRCS tWP tWP tWP tOEA tOEZ tOEA tOEZ tOEA tOEZ OE tRAC tCAC tAA tCAC tCAC tDH tAA tDH tAA tDH tCLZ tDS tCLZ tDS tCLZ tDS DQ0 - 7
Out In Out In Out In
tRAC
tCAC tAA
tDH
tDS
tCAC tAA tDS
Out
tDH
tDH tCAC tAA tDS
Out In
DQ8 - 15
tCLZ
Out
In
tCLZ
In
tCLZ
"H" or "L"
17/22
Semiconductor
CAS before RAS Refresh Cycle
RAS
UCAS LCAS
A0 - A8
WE
OE
DQ0 - 7
DQ8 - 15
,,,,
MSM5416126A
tRC tRP tRAS tRP tRPC tCSR tCHR tRPC
Inhibit Falling Transition
tOFF
Open
tOFF
Open
"H" or "L"
18/22
Semiconductor Hidden Refresh Cycle
MSM5416126A
,, , ,,
tRC tRAS tRP tRAS RAS tCRP tRCD tRSH UCAS LCAS tCHR tAR tRAD tRAL tASR tRAH tASC tCAH A0 - A8 Row Column tRCS tRRH WE tROH tOEA tOEZ OE tRAC tCAC tOFF tAA DQ0 - 7 Open Valid Data tRAC tCAC tAA tOFF DQ8 - 15 Open Valid Data "H" or "L"
19/22
Semiconductor
RAS Only Refresh Cycle
RAS
UCAS LCAS
A0 - A8
WE
OE
DQ0 - 7 DQ8 - 15
,,,,
MSM5416126A
tRC tRAS tRP tCRP tRPC tASR tRAH Row Open Open "H" or "L"
20/22
Semiconductor
MSM5416126A
PACKAGE DIMENSIONS
(Unit : mm)
SOJ40-P-400-1.27
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.70 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
21/22
Semiconductor
MSM5416126A
(Unit : mm)
TSOPII44/40-P-400-0.80-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.49 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
22/22
E2Y0002-29-11
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents cotained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation.
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Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan

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